Added all pinephone kernels

sys-kernel/pinephone-sources/files/megi-switch-parent-of-MIPI-DSI.patch

@@ -0,0 +1,44 @@
+From 2af59597979e0192cb4675c12e57ed2a857fe9ce Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman
+Date: Wed, 7 Oct 2020 02:11:35 +0200
+Subject: clk: sunxi-ng: sun50i-a64: Switch parent of MIPI-DSI to periph0(1x)
+
+This makes video0(1x) clock less constrained, and improves compatibility
+with external monitors on Pinephone when using both internal display
+and HDMI output at once.
+
+Signed-off-by: Ondrej Jirman <megous@megous.com>
+Modified by: Philip Müller <philm@manjaro.org>
+---
+ drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 11 ++++++++++-
+ 1 file changed, 10 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+index 8ac40a78e75e..e41eadc602e7 100644
+--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
++++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+@@ -969,6 +969,8 @@ static struct ccu_rate_reset_nb sun50i_a
+ 	.common		= &pll_video0_clk.common,
+ };
+ 
++#define CCU_MIPI_DSI_CLK 0x168
++
+ static int sun50i_a64_ccu_probe(struct platform_device *pdev)
+ {
+ 	struct resource *res;
+@@ -990,6 +992,12 @@ static int sun50i_a64_ccu_probe(struct p
+ 	writel(0x10040000, reg + SUN50I_A64_PLL_AUDIO_BIAS_REG);
+ 
+ 	writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);
++	
++	/* Set MIPI-DSI clock parent to periph0(1x), so that video0(1x) is free to change. */
++	val = readl(reg + CCU_MIPI_DSI_CLK);
++	val &= 0x30f;
++	val |= (2 << 8) | ((4 - 1) << 0); /* M-1 */
++	writel(val, reg + CCU_MIPI_DSI_CLK);
+ 
+ 	/* Force the parent of TCON0 to PLL-MIPI */
+ 	val = readl(reg + SUN50I_A64_TCON0_REG);
+-- 
+cgit v1.2.3
+